Overview
The PCB Editor provides comprehensive tools for:- Footprint placement and organization
- Interactive and automatic routing
- Copper zone management
- Design rule checking (DRC)
- 3D visualization
- Manufacturing file generation (Gerbers, drill files)
Interface Layout
Canvas and Layers
The main design area supports:- Multiple copper layers (2-32 layers)
- Technical layers (silkscreen, soldermask, paste)
- User documentation layers
- High-contrast mode for active layer focus
Key Panels
Appearance Controls
Appearance Controls
Layer Management:
- Show/hide individual layers
- Adjust layer transparency
- Set rendering options
- Configure color schemes
- Footprints (THT, SMD, Virtual)
- Tracks, vias, zones
- Text and graphics
- Ratsnest (air wires)
Selection Filter
Selection Filter
Control what objects can be selected:
- Filter by object type
- Filter by layer
- Locked items
- Quick toggle buttons
Properties Panel
Properties Panel
Edit selected objects:
- Footprint properties
- Track and via parameters
- Zone settings
- Text attributes
- Dimension properties
Net Inspector
Net Inspector
Analyze net characteristics:
- Net list with statistics
- Length, via count
- Filter and sort
- Highlight nets
Design Blocks
Design Blocks
Reusable PCB layouts:
- Place design blocks
- Create from selection
- Link to library
- Update instances
Toolbar Functions
- Top Main Toolbar
- Top Auxiliary Toolbar
- Right Toolbar
- Left Toolbar
- Update PCB from Schematic: Import netlist changes
- Save / Save As
- Print / Plot
- Undo / Redo
- Zoom controls
- 3D Viewer: Launch 3D view
- DRC: Run design rule check
- Layer pair selection
PCB Design Workflow
Importing from Schematic
Update PCB from Schematic
Review Changes
See additions, deletions, and modifications:
- New footprints to add
- Nets changed
- Components removed
- Footprint associations updated
Footprint Placement
Placement Strategies
Manual Placement
Full control over component positions:
- Click and drag
- Precise coordinates
- Alignment tools
- Grid snapping
Auto-Placement
Automatic component arrangement:
- Optimize by connectivity
- Place off-board first
- Respect keep-out areas
- Minimize wire length
Footprint Operations
| Action | Shortcut | Description |
|---|---|---|
| Place Footprint | A or O | Add from library |
| Move | M | Reposition |
| Rotate | R | Rotate 90° |
| Flip | F | Mirror to other side |
| Edit Properties | E | Modify parameters |
| Duplicate | Ctrl+D | Copy with offset |
| Delete | Del | Remove from board |
Board Outline
Defining Board Shape
Board outline must be drawn on the Edge.Cuts layer
- Draw Line segments
- Draw Arc
- Draw Rectangle
- Draw Circle
- Draw Polygon
- Import DXF/SVG
Ensure the outline is a closed polygon with no gaps
Routing
Interactive Router
KiCad’s modern push-and-shove router:- Routing Modes
- Routing Settings
Highlight Mode: Shows obstacles
- Useful for planning
- No collision avoidance
- Smart obstacle avoidance
- Automatically adjusts existing routes
- Maintains existing routing
- Finds path around obstructions
Differential Pairs
Setup
Setup
- Define differential pairs in schematic:
- Name signals with
+and-suffix (e.g.,USB_D+,USB_D-)
- Name signals with
- Configure net class rules
- Set coupling constraints
Routing
Routing
- Use “Route Differential Pair” tool
- Maintains spacing and length matching
- Supports meanders for tuning
Length Tuning
Meander Tool for matched lengths:- Set target length
- Adjust amplitude and spacing
- Visual feedback on current length
- Auto-tune to target
Copper Zones
Creating Zones
Configure Properties
- Layer assignment
- Net connection
- Fill settings (solid, hatched)
- Thermal relief parameters
- Priority level
Zone Fill Settings
Zone Properties
Design Rule Check (DRC)
Running DRC
Checks Include:- Clearance violations
- Track width violations
- Via size issues
- Drill to copper clearance
- Courtyard overlaps
- Silkscreen on pads
- Missing connections
- Isolated copper
DRC Configuration
Set rules in File → Board Setup → Design Rules:Net Classes
Define rules per net class:
- Track width
- Clearance
- Via sizes
- Differential pair settings
Constraints
Global design constraints:
- Minimum track width
- Minimum via size
- Micro via parameters
- Hole to hole spacing
Layer Stack Manager
Configuring Layers
Access via File → Board Setup → Board StackupCopper Layers
Copper Layers
- 2 to 32 layer boards
- Name each layer
- Set copper thickness
- Impedance control
Dielectric Layers
Dielectric Layers
- Core and prepreg
- Material selection
- Thickness specification
- Loss tangent for RF
Surface Finish
Surface Finish
- Soldermask color and type
- Silkscreen color
- Surface finish (HASL, ENIG, etc.)
3D Viewer Integration
Launching 3D View
Press
Alt+3 or click the 3D Viewer button- Realistic board rendering
- Component 3D models
- Ray-tracing mode
- Export STEP/VRML
- Mechanical clearance checking
Manufacturing Outputs
Gerber Files
Select Layers
Check layers to export:
- Copper layers
- Soldermask (F.Mask, B.Mask)
- Silkscreen (F.Silks, B.Silks)
- Paste (F.Paste, B.Paste)
- Edge.Cuts
Other Export Formats
- IPC-2581
- ODB++
- STEP
Modern intelligent CAD format:
- Single file with all data
- Includes stackup
- Better than Gerber for complex boards
Advanced Features
Generators
Generators are parametric objects that automatically update
- Via stitching
- Track meandering
- Teardrops
- Microwave structures
Scripting with Python
Example: Move all resistors
Multi-Channel Design
Repeat Layout
Replicate circuit blocks:
- Identify source rule area
- Generate instances
- Maintain relative positions
Generate Rules
Auto-create rule areas:
- From hierarchical sheets
- For repeating subcircuits
- Simplifies updates
Keyboard Shortcuts
Essential Shortcuts
| Action | Shortcut |
|---|---|
| Place Footprint | A or O |
| Route Track | X |
| End Track | End |
| Add Via | V |
| Switch Layer | + / - |
| Fill Zones | B |
| Highlight Net | ` |
| Measure | Ctrl+Shift+M |
| Flip | F |
| Rotate | R |
| Move Exactly | Ctrl+M |
| Duplicate | Ctrl+D |
| Delete | Del |
| Edit Properties | E |
Best Practices
Related Topics
3D Viewer
Visualize board in 3D
Gerber Viewer
Inspect manufacturing files
Design Rules
Configure DRC constraints