Type Definitions
Instructions are defined using Python type hints inproblem.py:
From
problem.py:14-15 - An instruction is a dictionary mapping engine names to lists of operation tuples.Instruction Structure
Each instruction is a VLIW (Very Large Instruction Word) bundle that specifies operations for multiple engines:Key Principles
Parallel Execution
Parallel Execution
All operations within an instruction execute in parallel during a single cycle. Each engine processes all its slots simultaneously.
Slot Limits
Slot Limits
Each engine has a maximum number of operations it can execute per cycle:
- ALU: 12 slots
- VALU: 6 slots
- LOAD: 2 slots
- STORE: 2 slots
- FLOW: 1 slot
- DEBUG: 64 slots (doesn’t count as a cycle)
End-of-Cycle Semantics
End-of-Cycle Semantics
All writes take effect at the end of the cycle after all reads complete. This means you can safely read and write the same location in one instruction - the read sees the old value.
Operand Format
Scratch Addresses
Most operands reference locations in scratch memory:Exceptions
| Operation | Exception | Description |
|---|---|---|
const | Second operand is immediate | ("const", dest, 42) - dest gets value 42 |
add_imm | Third operand is immediate | ("add_imm", dest, src, 5) - adds 5 to src |
jump | Operand is instruction index | ("jump", 10) - jumps to instruction 10 |
cond_jump | Second operand is instruction index | ("cond_jump", cond, 10) |
cond_jump_rel | Second operand is offset | ("cond_jump_rel", cond, -5) - jumps back 5 instructions |
store | First operand is indirect | ("store", addr, src) - stores to mem[scratch[addr]] |
From
problem.py:86-94 - The machine documentation states: “In general every number in an instruction is a scratch address except for const and jump, and except for store and some flow instructions the first operand is the destination.”Destination Convention
For most operations, the first operand is the destination:Vector Operations
Vector operations work on 8 contiguous scratch addresses (VLEN=8):
When you specify address 100 for a vector operation, it operates on addresses 100, 101, 102, 103, 104, 105, 106, 107.
Example Instruction Bundles
Simple Arithmetic
Memory Operations
Vector Processing
Conditional Execution
Loop Control
VLIW Packing Strategy
Packing Example
Poor packing (4 cycles):Dependency Example
Must use 2 cycles (second operation depends on first):Real-World Example from build_kernel
Here’s a typical instruction from the hash computation:This example shows VLIW packing: multiple independent operations (load constant, XOR, two shifts) execute in parallel in a single cycle.
Debugging Instructions
Related
Engine Reference
Detailed operation reference for each engine
Architecture Guide
Understanding VLIW and SIMD concepts
Writing Kernels
How to write efficient kernel code
Machine Class
Machine simulator implementation