CPU Architecture

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Xbox 360 CPU

• Architecture: PowerPC 64-bit (running in 32-bit mode)
• Cores: 3 cores, each with 2 hardware threads (6 logical processors)
• Clock Speed: 3.2 GHz
• Instruction Set: PowerPC with AltiVec (VMX) and VMX128 extensions
• Registers: 64-bit general purpose and vector registers

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JIT Translation Pipeline

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Phase 1: Translation to HIR

• Scanner (src/xenia/cpu/ppc/ppc_scanner.h) - Analyzes code to find basic blocks and functions
• HIR Builder (src/xenia/cpu/ppc/ppc_hir_builder.h) - Constructs HIR from PowerPC instructions
• Emitters (src/xenia/cpu/ppc/ppc_emit_*.cc) - Per-instruction translation logic

• ppc_emit_control.cc - Branch, call, and control flow instructions
• ppc_emit_alu.cc - Integer arithmetic and logical operations
• ppc_emit_fpu.cc - Floating-point operations
• ppc_emit_altivec.cc - Vector (AltiVec/VMX) instructions

PowerPC:  add r3, r4, r5
HIR:      v0 = load_context offset=GPR[4]
          v1 = load_context offset=GPR[5]
          v2 = add v0, v1
          store_context offset=GPR[3], v2

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Phase 2: HIR Optimization

1. Control Flow Analysis - Builds control flow graph (CFG)
2. Control Flow Simplification - Merges blocks and removes dead branches
3. Context Promotion - Promotes frequently-used context values to registers
4. Simplification + Constant Propagation (loop until no changes)
   • Simplifies expressions and eliminates redundant operations
   • Propagates constants through expressions
5. Memory Sequence Combination - Combines adjacent loads/stores
6. Dead Code Elimination - Removes unused instructions
7. Value Reduction - Simplifies value representations

• Context Promotion - PowerPC registers are stored in a context structure. This pass promotes hot registers to x64 registers, avoiding memory loads/stores.
• Constant Propagation - Detects compile-time constants and folds them into instructions
• Dead Store Elimination - Removes writes to memory/registers that are never read

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Phase 3: Backend Code Generation

• x64 Backend (src/xenia/cpu/backend/x64/x64_backend.cc) - Main backend implementation
• x64 Sequences (src/xenia/cpu/backend/x64/x64_sequences.cc) - HIR to x64 instruction sequences
• x64 Emitter (src/xenia/cpu/backend/x64/x64_emitter.cc) - Generates actual x64 machine code
• Code Cache (src/xenia/cpu/backend/x64/x64_code_cache.cc) - Stores compiled code

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x64 ABI and Register Mapping

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Transition Thunks

1. Host → Guest: Saves host registers, loads guest context, jumps to JIT code
2. Guest → Host: Saves guest context, restores host registers, returns

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Register Allocation

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Integer Registers

• RSI always points to the PowerPC context structure (guest registers)
• RDI always points to the base of guest virtual memory

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Floating Point Registers

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Calling Convention

• Parameters: r3-r10 (additional on stack)
• Return value: r3 (32-bit) or r3:r4 (64-bit)
• Floating point: f1-f13 for parameters

• SHIM_GET_ARG_32(n) - Reads from r3+n
• SHIM_SET_RETURN_32(v) - Writes to r3

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Memory Access

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Virtual Memory

PowerPC:  lwz r3, 0x100(r4)     # Load word from r4+0x100

x64:      mov ecx, [rsi+GPR[4]]  # Load r4 from context
          mov eax, [rdi+rcx+0x100] # Load from memory (RDI=membase)
          mov [rsi+GPR[3]], eax   # Store to r3 in context

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Memory Barriers

• sync - Memory barrier
• isync - Instruction synchronization
• eieio - Enforce in-order execution of I/O

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Code Cache

• Functions are compiled once and cached
• Cache is searched by guest address before recompiling
• Generated code is stored in executable memory pages
• On Windows and POSIX, uses platform-specific memory APIs for RWX pages

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System Call Handling

1. Loader replaces kernel import with sc (syscall) instruction
2. JIT detects syscall and emits call to kernel export handler
3. Execution transitions from guest to host
4. Kernel export (native C++) executes
5. Return value is placed in r3
6. Execution returns to guest code

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Multi-threading

• Each guest thread runs on a host thread
• Thread scheduling is handled by the host OS
• Synchronization primitives (mutexes, events) are implemented in kernel
• Lock-free atomic operations translate to x64 lock prefix instructions

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Performance Considerations

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JIT Compilation Overhead

• First execution of a function incurs compilation cost
• Subsequent calls execute cached native code
• Hot functions compile quickly (< 1ms typically)
• Games with large code bases may have longer initial loads

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Optimization Trade-offs

• More optimization passes improve code quality but increase compile time
• Context promotion is critical for performance (avoids memory traffic)
• Some passes can be disabled for faster compilation (e.g., --disable_context_promotion)

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Accuracy vs Speed

• CPU timing is not cycle-accurate
• Branch prediction behavior differs from real hardware
• Most games don’t depend on exact timing
• Games with tight timing loops may have issues

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Debugging and Analysis

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HIR Dumping

• Understanding translation issues
• Analyzing optimization effectiveness
• Debugging crashes in generated code

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Disassembly

• Set breakpoints in JIT code
• Single-step through generated instructions
• Compare with original PowerPC disassembly

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References

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PowerPC Architecture

• Free60 Xenon CPU Info
• Power ISA Specification
• PowerPC Programming Environments Manual
• AltiVec Programming Environment Manual
• VMX128 Opcodes

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x64 Architecture

• Intel Software Developer Manuals
• Apple AltiVec/SSE Migration Guide