PE

​

Module declaration

module pe #(
    parameter int DATA_WIDTH = 16
) (
    input logic clk,
    input logic rst,
    // North ports
    input logic signed [15:0] pe_psum_in,
    input logic signed [15:0] pe_weight_in,
    input logic pe_accept_w_in,
    // West ports
    input logic signed [15:0] pe_input_in,
    input logic pe_valid_in,
    input logic pe_switch_in,
    input logic pe_enabled,
    // South ports
    output logic signed [15:0] pe_psum_out,
    output logic signed [15:0] pe_weight_out,
    // East ports
    output logic signed [15:0] pe_input_out,
    output logic pe_valid_out,
    output logic pe_switch_out
);

​

Parameters

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Input ports

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North ports (from PE above or top of array)

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West ports (from PE to the left or left edge of array)

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Output ports

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South ports (to PE below or bottom of array)

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East ports (to PE to the right or right edge of array)

​

Architecture

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Weight buffering

• Active register (weight_reg_active): Used for current computation
• Shadow register (weight_reg_inactive): Holds next set of weights

​

MAC operation

1. Multiply: mult_out = pe_input_in × weight_reg_active
2. Accumulate: mac_out = mult_out + pe_psum_in
3. Output: pe_psum_out = mac_out (when pe_valid_in is high)

​

Fixed-point arithmetic

• Multiplication: fxp_mul module (~https://github.com/tiny-tpu-v2/tiny-tpu/blob/main/src/fixedpoint.sv:278)
• Addition: fxp_add module (~https://github.com/tiny-tpu-v2/tiny-tpu/blob/main/src/fixedpoint.sv:110)

​

Signal flow diagram

        North
          ↓
      [psum_in]
     [weight_in]
   [accept_w_in]
          |
 West → [PE] → East
 [input]  |  [input]
 [valid]  |  [valid]
[switch]  |  [switch]
          ↓
       [psum_out]
     [weight_out]
        South

​

Operation sequence

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Weight loading phase

1. Assert pe_accept_w_in high
2. Drive pe_weight_in with weight value
3. On clock edge, weight loads into weight_reg_inactive
4. Weight propagates to pe_weight_out for PE below

​

Weight switching phase

1. Assert pe_switch_in high
2. Combinationally (same cycle), weight_reg_active ← weight_reg_inactive
3. Switch signal propagates east

​

Computation phase

1. Drive pe_input_in with activation value
2. Assert pe_valid_in high
3. On clock edge:
   • PE computes MAC operation
   • pe_psum_out = pe_psum_in + (pe_input_in × weight_reg_active)
   • Input and valid signals propagate east

​

Example instantiation

pe pe11 (
    .clk(clk),
    .rst(rst),
    .pe_enabled(pe_enabled[0]),
    .pe_valid_in(sys_start),
    .pe_valid_out(pe_valid_out_11),
    .pe_accept_w_in(sys_accept_w_1),
    .pe_switch_in(sys_switch_in),
    .pe_switch_out(pe_switch_out_11),
    .pe_input_in(sys_data_in_11),
    .pe_psum_in(16'b0),
    .pe_weight_in(sys_weight_in_11),
    .pe_input_out(pe_input_out_11),
    .pe_psum_out(pe_psum_out_11),
    .pe_weight_out(pe_weight_out_11)
);

​

Timing behavior

• Weight loading: Registered (sequential, 1 cycle)
• Weight switching: Combinational (0 cycles)
• MAC operation: Registered (sequential, 1 cycle)
• Signal propagation: Registered (sequential, 1 cycle)

​

Related modules

• Systolic Array - PE array organization
• Fixed-point library (~https://github.com/tiny-tpu-v2/tiny-tpu/blob/main/src/fixedpoint.sv) - Arithmetic modules

​

Testing

• ~https://github.com/tiny-tpu-v2/tiny-tpu/blob/main/test/dump_pe.sv - Waveform dump configuration
• ~https://github.com/tiny-tpu-v2/tiny-tpu/blob/main/test/test_pe.py - Python test suite